Timing generating circuit and method

摘要

PCT No. PCT/JP95/00070 Sec. 371 Date Sep. 20, 1996 Sec. 102(e) Date Sep. 20, 1996 PCT Filed Jan. 24, 1995A timing generating circuit formed as an LSI of CMOS.FETs is provided which enables correction of the variations of delay amount caused by the heat generated in the CMOS.FETs due to the propagation of pulses through the CMOS.FETs. A sub delay element 22 is connected in series to a main delay element 21 in which a timing is set and placed in the vicinity of the element 21. Both delay elements are connected in the same cell structure and arrangement. The sum of initial values of the delay amounts of respective delay elements is made to be a constant value. An input pulse to the main delay element is also supplied to a reference signal generator part 27 which outputs a reference signal using a reference clock after the lapse of the constant value from the time the input pulse is inputted. A time difference between this reference signal and the output from the sub delay element 22 is detected by a time difference detection part 29. Correcting amounts are calculated by splitting this time difference in accordance with the ratio of the initial values of the delay amounts. The delay amounts of the delay elements 21 and 22 are then corrected with the correcting amounts, respectively, such that the sum comes to the constant value.