| 摘要 |
<p>PROBLEM TO BE SOLVED: To generate a stable clock signal and to enable stable and high efficiency read-out operation and write-in operation of data without being affected by operation voltage. SOLUTION: A constant current is generated by a current mirror circuit CM, and constant voltage VRSYS is generated by a resistor R. A comparator CP1 compares the constant voltage VRSYS with voltage of a node A of a capacitor C1, when voltage of the node A is higher than the constant voltage VRSYS, a clock signal CLK of multivibrators of NAND circuits ND1-ND4 becomes a HI signal, and a clock signal/CLK become Lo single. A comparator CP2 compares the constant voltage VRSYS with voltage of a node B of a capacitor C2, when voltage of the node B is higher than the constant voltage VRSYS, a clock signal/CLK of a multivibrator becomes a Hi signal. Thereby, a period of the clock signal CLK is decided by the resistor R and electrostatic capacity of capacitors C1, C2, these oscillation are repeated, and supplied as an internal clock.</p> |
