| 摘要 |
<p>PROBLEM TO BE SOLVED: To eliminate the need of adding a synchronizing signal to all response signals and to improve the efficiency of communication between transmission/ reception by permitting a transmission side to transmit transmission data in accordance with an inner reference signal, and permitting a reception side to generate a clock based on a transmission signal and to send the response signal to the transmission side in synchronizing with the clock. SOLUTION: A PLL circuit 8 phase-synchronizes the output clock with a reception signal. A shaping circuit 11 samples the reception signal at a sample clock and holds the value. When a SYNC circuit 10 receives the prescribed quantity of received bit strings matched with a synchronizing signal pattern, the PLL circuit 8 is locked and the output of the matching circuit 11 is written in a memory 9 in synchronizing with a bit clock Bitclk'. At the time of returning the response signal after reception terminates, the response signal is transmitted in synchronizing with the bit clock Bitclk'. On the other hand, the transmission side samples the response signal in accordance with the reception timing of the response signal.</p> |
