摘要 |
<p>PROBLEM TO BE SOLVED: To identify accurate logic '1'/'0' by conducting sampling by a clock signal in the middle of input data at all times even when duty of a pulse is fluctuated with respect to the retiming circuit. SOLUTION: The retiming circuit is provided with a delay means 25 that gives a variable delay to input data or a clock, a reference clock generating means 23 that generates a reference clock synchronously with the clock, a 1st phase difference detection means 21 that detects a phase difference between a leading of the reference clock and a leading of the input data, a 2nd phase difference detection means 22 that detects a phase difference between a trailing of the reference clock and a trailing of the input data, and an intermediate phase setting means 24 that calculates an intermediate phase of the input data based on the outputs of the 1st and 2nd phase difference detection means and controls a delay based on the intermediate phase.</p> |