| 摘要 |
<p>PROBLEM TO BE SOLVED: To simplify address setting for each operation at the time of verifying and control flag setting by a program by cutting off carry of nth bit and (n+1)th bit in order of receiving data at the time of write-in, and permitting carry of nth bit and (n+1)th bit at the time of verifying, in an address generating circuit. SOLUTION: In an address generating circuit, after an address initial value is set to an address register, a counter loads the value, 1 is successively added to an address initial value, and a write-in address is outputted to a non-volatile memory-1. The counter generates an address of 4 bits by connecting flip-flop by four stages. The counter is same as an ordinary counter, but selects a data latch signal at the time of write-in as a count clock and selects a write-in signal of a data register at the time of verifying, and a signal for carrying from the second bit to the third bit counting from the lowest order is effective only at the time of verifying.</p> |
