发明名称 |
COMMON BUFFER SWITCH |
摘要 |
<p>PROBLEM TO BE SOLVED: To attain traffic control with a high efficiency without remarkable increase in number of cell buffer address pointer FIFO sets. SOLUTION: A common buffer control section 8 acquires a cell buffer address FIFO number to be in use, acquires an address at which a cell is stored in a common buffer 4 from an idle address FIFO 10, a header and a payload of the cell transferred to the common buffer 4 are written in the common buffer 4 and an address acquired from the idle address FIFO 10 is queued in cell buffer address pointers FIFO 111 -11n corresponding to the address acquired from the idle address FIFO 10. A cell address stored in the cell buffer address pointers FIFO 111 -11n is read based on a cell output timing of the common buffer control section 8 and on the queued cell to read a cell stored in the common buffer 4 and the cell is outputted with higher priority as the class of higher level.</p> |
申请公布号 |
JPH11122257(A) |
申请公布日期 |
1999.04.30 |
申请号 |
JP19970281930 |
申请日期 |
1997.10.15 |
申请人 |
HITACHI LTD;HITACHI INFORMATION TECHNOLOGY CO LTD |
发明人 |
MATSUYAMA NOBUHITO;OTANI TSUGURO;SUKAI KAZUO;ISE SEIJI;KAWAMURA SHUSUKE |
分类号 |
H04Q3/00;H04L12/28;(IPC1-7):H04L12/28 |
主分类号 |
H04Q3/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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