| 摘要 |
The circuit comprises at least three levels, of which each has a number of selectors with two inputs, which are operated in a predetermined minimum bit-width unit. The first level has a first amount of selectors, which corresponds to a quotient of a division of the input bit-width through the minimum bit-width unit. The second level and the third level have an amount of selectors, corresponding to half of the first amount. The circuit comprises at least three levels, of which each has a number of selectors with two inputs, which are operated in a predetermined minimum bit-width unit. The circuit has two inputs with a predetermined input bit-width. The first level has a first amount of selectors, which corresponds to a quotient of a division of the predetermined input bit-width through the predetermined minimum bit-width unit. The second level has a second amount of selectors, corresponding to half of the first amount, so that their inputs receive half of the outputs of the first level. The third level has a third amount of selectors, corresponding to the half of the first amount in such way, that their inputs receive both a half of the outputs of the second level, as well as a half of the outputs of a remaining half group of the first level.
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