A timing circuit for recording the duration of intervals between a plurality of events in a data stream, comprising at least two timing channels, each arranged to generate a signal representing time elapsed between events. The rate of change of the signal generated by each timing channel varies with increasing interval duration, and the timing channels are arranged such that each event terminates the operation of one timing channel and initiates operation of another timing channel.
申请公布号
WO9921063(A1)
申请公布日期
1999.04.29
申请号
WO1998GB03093
申请日期
1998.10.16
申请人
THE VICTORIA UNIVERSITY OF MANCHESTER;LLOYD, CHRISTOPHER, JAMES;CLARKE, DAVID, JOHN