发明名称 CAD for redundant memory devices
摘要 <p>A memory device generator for generating memory devices in a CAD environment, the generator comprising: a library means (4) containing predefined basic circuit components; memory array generation means (2) interacting with the library means (4) for generating a variable-size memory array (3) comprising a variable number of memory elements (R,C), and at least one redundant memory element (RR0-RR6); memory element selection circuit generation means (6,9,30) interacting with the library means (4) for generating a memory element selection circuit (7,10;7,10-1 to 10-n) to be associated with the memory array for selecting at least one memory element according to memory device address inputs (RADD,CADD). The memory element selection circuit generation means (6,9,30) comprises means for generating a variable-size content-addressable memory means (7,10;7,10-1 to 10n) having a plurality of content-addressable memory locations (8,12) each one associated to at least one respective memory element (R,C) or to the at least one redundant memory element (RR0-RR6), each of the content-addressable memory locations suitable for storing one of a set of values of the memory device address inputs and for selecting the respective memory element or redundant memory element when the memory device address inputs take the one value. &lt;IMAGE&gt;</p>
申请公布号 EP0911747(A1) 申请公布日期 1999.04.28
申请号 EP19970830525 申请日期 1997.10.20
申请人 STMICROELECTRONICS S.R.L. 发明人 CAPOCELLI, PIERO;TALIERCIO, MICHELE;VARAMBALLY, RAJAMOHAN;BARONI, ANDREA
分类号 G11C29/00;(IPC1-7):G06F17/50;G06F11/20 主分类号 G11C29/00
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