发明名称 |
Pseudo-random address generation mechanism that reduces address translation time |
摘要 |
It is known that virtual memory segments that are allocated together tend to be used together. With existing sequential address allocation mechanisms, this in turn means that programs tend to end up using the same set or sets of virtual segment addresses (i.e., in the same minitable or minitables), which, as mentioned, leads to increased address translation time because of clumping. The address allocation mechanism of the present invention reduces clumping by allocating virtual segment addresses in a pseudo-random order. This decreases the likelihood that virtual segment addresses that are allocated together end up in the same set or sets of virtual segment addresses within the address translation table.
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申请公布号 |
US5897662(A) |
申请公布日期 |
1999.04.27 |
申请号 |
US19950517759 |
申请日期 |
1995.08.18 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CORRIGAN, MICHAEL JOSEPH;LEVENSTEIN, SHELDON BERNARD;STEWART, TERRENCE JAMES |
分类号 |
G06F12/10;(IPC1-7):G06F12/02 |
主分类号 |
G06F12/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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