发明名称 Multilayer interconnection technique
摘要 A multilayer wiring structure consists of a substrate with a first set of wiring lines formed thereon. A first insulating layer covers the first set of wiring lines, a second insulating layer covers the first set of wiring lines and then a second set of wiring lines are formed on the second insulating layer. Vias are formed through the second insulating layer, the second wiring lines and the first insulating layer extending down to the surface or near the surface of the first wiring lines. Metallizations fill the vias to form connections and interconnections to and between the first wiring lines, the second wiring lines and the surface of the semiconductor device. Additional wiring lines may be formed on the surface of the second insulating layer and in contact with the metallizations.
申请公布号 US5897342(A) 申请公布日期 1999.04.27
申请号 US19960752212 申请日期 1996.11.19
申请人 UNITED MICROELECTRONICS CORP. 发明人 LIU, CHUN-SHENG;HSU, CHEN-CHUNG;HUANG, TSUY-HUA
分类号 H01L21/768;H01L23/522;(IPC1-7):H01L21/82 主分类号 H01L21/768
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