| 摘要 |
A semiconductor manufacturing process comprising providing a semiconductor substrate, forming a gate dielectric on an upper surface of the semiconductor substrate, forming a conductive gate on an upper surface of the gate dielectric, forming a first pair of spacer structures on the first and second sidewalls of the conductive gate, introducing a first source impurity distribution into the semiconductor substrate, forming a second pair of spacer structures on respective exterior sidewalls on the first pair of spacer structures, and introducing a drain impurity distribution into the detached drain region of the semiconductor substrate. The semiconductor substrate includes a channel region laterally displaced between a first source region and a detached drain region. The conductive gate includes a first and a second sidewall. Exterior sidewalls of the first pair of spacer structures are displaced from the first and second sidewalls of the conductive gate by a source displacement. A channel boundary of the first source region is laterally displaced from the second sidewall of the conductive gate by the source displacement. Exterior sidewalls of the second pair of spacer structures are laterally displaced from the first and second sidewalls of the conductive gate by a drain displacement. A channel boundary of the detached drain region is laterally displaced from the first sidewall of the conductive gate by the drain displacement. The conductive gate may comprise heavily doped CVD polysilicon or, alternatively, the conductive gate may be formed from a metal such as aluminum, copper, tungsten, or alloys thereof.
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