发明名称 Method and apparatus for bit cell ground choking for improved memory write margin
摘要 A method and apparatus to increase the size of the design window for write margin and read stability margin of memory cells without requiring a voltage above the power supply voltage or below ground. An SRAM consisting of an SRAM cell having a ground reference and a circuit coupled to receive a first signal and coupled to drive the ground reference. The circuit is configured to drive the ground reference to a first voltage if the first signal is in a first state. The circuit is configured such that the first node is at a second voltage if the first signal in a second state, the first signal being in the first state indicating a write operation, the first signal being in the second state indicating a non-write operation, the first voltage being greater than the second voltage.
申请公布号 US5898610(A) 申请公布日期 1999.04.27
申请号 US19960775796 申请日期 1996.12.31
申请人 INTEL CORPORATION 发明人 GREASON, JEFFREY K.
分类号 G11C11/412;(IPC1-7):G11C11/00 主分类号 G11C11/412
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