发明名称 Memory access mechanism for a parallel processing computer system with distributed shared memory
摘要 To increase the capacity of usable memory of a parallel processing computer system as a whole and effectively utilize the address space without waste, a variable-length Global/Local allocation field is provided in a fixed-length address. When the field is locally set, the address is used as an address of a local memory area to which the local processor refers. When the allocation is globally set, the remaining address is a variable length logical processor number (this number is converted into a physical processor number) and a variable length offset address, for specifying a global memory area belonging to a processor out of the global areas of memories of a group of some of the processors, which global memory can be referred to by all the processors of the groups. A memory access interface executes memory access to the local or global area of the memory of the local processor or to the global area of the memory of another processor.
申请公布号 US5898883(A) 申请公布日期 1999.04.27
申请号 US19950368618 申请日期 1995.01.04
申请人 HITACHI, LTD. 发明人 FUJII, HIROAKI;TARUI, TOSHIAKI;SUKEGAWA, NAONOBU
分类号 G06F15/17;G06F12/02;(IPC1-7):G06F15/16 主分类号 G06F15/17
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