发明名称 Parallel computer system with error status signal and data-driven processor
摘要 A parallel computer system includes a plurality of processing elements each comprising a network control unit. The network control unit of the processing element has ports to north, east, west and south, and row directional communication lines and column directional communication lines are connected to each port forming a taurus mesh network. Each processing element operates in two communication control modes, in a bi-directional communication mode or in a unidirectional communication mode. In the bi-directional communication mode, the network control unit permits eastward and westward transmission of data through the row directional communication lines and northward and southward transmission of data through the column directional communication lines. In the unidirectional communication mode, only the one way data transmission from west to east is permitted in the row directional communication lines, and only the one way data transmission from north to south is permitted in the column directional communication lines.
申请公布号 US5898881(A) 申请公布日期 1999.04.27
申请号 US19970848825 申请日期 1997.05.01
申请人 SANYO ELECTRIC CO., LTD 发明人 MIURA, HIROKI;KOUMURA, YASUHITO
分类号 G06F11/07;G06F15/173;G06F15/80;(IPC1-7):G06F15/80;G06F15/82 主分类号 G06F11/07
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