| 摘要 |
A data bus interface circuit is provided. The data bus interface circuit includes interface circuitry that can receive, store, and transmit data. Egress bus input circuitry is connected to the interface circuitry. The egress bus input circuitry receives incoming STM and ATM data from a first egress data bus. STM egress bus input circuitry is connected to the interface circuitry. The STM egress bus input circuitry transmits the incoming STM data over a second egress data bus. ATM egress bus input circuitry connected to the interface circuitry transmits the incoming ATM data over a third egress data bus. STM ingress bus input circuitry receives outgoing synchronous transfer mode data, and ATM ingress bus input circuitry receives outgoing asynchronous transfer mode data. Ingress bus output circuitry connected to the interface circuitry transmits outgoing STM and outgoing ATM data over a third ingress data bus. |
