摘要 |
<p>PROBLEM TO BE SOLVED: To replace a clock signal without production of missing bits even when fluctuation takes place in a write clock or a read clock. SOLUTION: While write, read clocks WCK, RCK are still unstable, serial input data DIN are written in a buffer memory 10 based on a write address from a counter 20. In the case that data are read from the memory 10 based on a read address from a counter 30, a phase comparator circuit 40 quickly detects that a phase difference margin between the write and read addresses is insufficient and, e.g. a counter 30 is initialized to have a desired count.</p> |