发明名称 BIT BUFFER DEVICE FOR CLOCK REPLACEMENT
摘要 <p>PROBLEM TO BE SOLVED: To replace a clock signal without production of missing bits even when fluctuation takes place in a write clock or a read clock. SOLUTION: While write, read clocks WCK, RCK are still unstable, serial input data DIN are written in a buffer memory 10 based on a write address from a counter 20. In the case that data are read from the memory 10 based on a read address from a counter 30, a phase comparator circuit 40 quickly detects that a phase difference margin between the write and read addresses is insufficient and, e.g. a counter 30 is initialized to have a desired count.</p>
申请公布号 JPH11112456(A) 申请公布日期 1999.04.23
申请号 JP19970269880 申请日期 1997.10.02
申请人 HITACHI COMMUN SYST INC 发明人 OTA YUJI
分类号 H04J3/06;H04L7/00;(IPC1-7):H04J3/06 主分类号 H04J3/06
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