| 摘要 |
PROBLEM TO BE SOLVED: To provide a synchronous delay circuit which eliminates the need of designing a clock driver dummy whenever the design of wiring is changed even if it is applied to a device where the clock delay quantity of ASIC (application specific integrated circuit) differs at every chip and which improves design efficiency and precision. SOLUTION: A first delay circuit string 1 advancing a pulse or a pulse edge for prescribed time, a second delay circuit string 2 which can make the pulse or the pulse edge pass through for length proportional to that where the pulse or the pulse edge travels through the first delay circuit and a latch delay circuit 5 storing and reproducing the delay time of a clock driver are provided. The delay quantity of tcK-(d1+d2) is obtained without the dummy of the clock driver by advancing the latch delay circuit 5 and the delay circuit string 1 in a clock period tcK. |
