发明名称 VARIABLE LENGTH DECODER AND VARIABLE LENGTH ENCODER
摘要 PROBLEM TO BE SOLVED: To attain reduction of a recording memory of 0 coefficient and a circuit by decoding data necessary for a DCT operation and storing, enabling write-in and read-in, preparing a write-in and read-out address, controlling a counter for preparing the address, and temporarily storing a write-in counter value and controlling an output of the last data. SOLUTION: When a pair of a RUN and an AMP inputted from a variable length decoder 101 are except EOB, it is written in a memory 102 and a write-in counter value is increment by 1. Next, the next pair is discriminated and if it is other than EOB, it is written in the memory 102 and the write-in counter value is made incremental by 1; in this way, the same operation is repeated until the EOB is inputted. The write-in counter value is held in a counter value memory 1:106. From the value of this memory 1:106, it is discriminated from which part of the memory data are read out, at the time of reading. When the EOB is detected, the counter is held as it is.
申请公布号 JPH11112933(A) 申请公布日期 1999.04.23
申请号 JP19970272567 申请日期 1997.10.06
申请人 SHARP CORP 发明人 AOKI KAZUYA
分类号 H04N5/92;H04N19/423;H04N19/426;H04N19/46;H04N19/60;H04N19/625;H04N19/70;H04N19/88;H04N19/91;H04N19/93 主分类号 H04N5/92
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