发明名称 CAD integrated circuit manufacturing method
摘要 The method involves forming at least one layer of electronic components and conductive tracks on a silicon substrate according to a fixed circuit plan. Tools e.g. masks are constructed to form the components, and conductive tracks with fixed technological basic data. The masks etc., are used in individual processes to form the circuit elements and conductive tracks on the substrate. The tools, e.g. masks are first manufactured virtually. Integrated circuits are then manufactured virtually in the frame of a computer simulation with the virtual masks. When the virtual circuit deviates from a theoretical optimal mask, the mask is adjusted. The virtual circuit is checked for maintaining minimum requirements, e.g. minimum and maximum dimensions. The integrated circuit and the required tools, e.g. mask are first manufactured when the minimum requirements are achieved with the virtual integrated circuit.
申请公布号 DE19738717(C1) 申请公布日期 1999.04.22
申请号 DE19971038717 申请日期 1997.09.04
申请人 SIEMENS AG, 80333 MUENCHEN, DE 发明人 ZELLNER, ANGELA, 80469 MUENCHEN, DE
分类号 G06F17/50;(IPC1-7):H01L21/77;H01L21/768 主分类号 G06F17/50
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