Digitale Verarbeitungsschaltung mit Prüfregistern

摘要

The processing circuit (9) used for treating images has a host interface (7) which allows its bus (6) access to and from an external information system (8). The processing circuits are divided into three blocks (1,2,3) connected by the bus (6). Test registers (4,5) are also connected to the bus (6) and interposed between upstream and downstream blocks. The test registers which have active and rest states are each identified by an address which enables data to be sent to them or the data stored in them to be read.