| 摘要 |
An apparatus for controlling access to a shared memory in a network system including at least one fast port interface circuit and at least one slow port interface circuit (206). Each fast port interface circuit comprises a first input port interface (208) which sequentially receives data, address, and command information from a network client at a first data rate in segments of a first width. This data and address information is stored until it is read out in parallel to a shared memory in response to command. The slow port interface circuit (206) receives data, address, and command information from a network client at a second data rate in segments of the first width and transmits the data, address, and command information to a storage circuit that is shared among the slow, port interface circuits. The shared storage circuit comprises a plurality of slow interface registers which sequentially store the segments of data in one of the slow interface registers at the same time the contents of another slow interface register are read out in parallel to the shared memory. |
