发明名称 |
Mapping heterogeneous logic elements in a programmable logic device |
摘要 |
<p>A disclosed method and mechanism provides for the mapping of heterogeneous logic elements in a programmable logic device. a method and mechanism for mapping heterogeneous logic elements in a portion of electronic design compilation for a programmable integrated circuit is disclosed. Specifically, the invention provides a method to perform the technology mapping of heterogeneous logic elements in a programmable logic device such as selectively choosing the best combination of product term logic elements and look up table logic elements. <IMAGE></p> |
申请公布号 |
EP0910027(A2) |
申请公布日期 |
1999.04.21 |
申请号 |
EP19980308491 |
申请日期 |
1998.10.16 |
申请人 |
ALTERA CORPORATION |
发明人 |
LEAVER, ANDREW;HEILE, FRANCIS |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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