发明名称 |
Multiple instruction decoder |
摘要 |
<p>A multiple instruction decoder is disclosed that employs arbitration to reduce port contentions for M available read ports by N register-operands where M is less than N. In particular, the disclosed multiple instruction decoder includes an input latch for receiving a plurality of logic instructions, wherein the plurality of logic instructions include N register-operand identifiers; arbitration logic coupled to the input latch for arbitrating read port contentions by the N register-operand identifiers for M available read ports (where M is less than N) based on arbitration data corresponding to each of the logic instructions, and for generating control signals indicative thereof; and a multiplexing unit for selectively supplying the N register-operand identifiers to the M available read ports in response to the control signals generated by the arbitration logic.</p> |
申请公布号 |
EP0411747(B1) |
申请公布日期 |
1999.04.21 |
申请号 |
EP19900305724 |
申请日期 |
1990.05.25 |
申请人 |
ADVANCED MICRO DEVICES, INC. |
发明人 |
JOHNSON, WILLIAM MICHAEL |
分类号 |
G06F9/34;G06F9/38;G06F9/30;(IPC1-7):G06F9/38 |
主分类号 |
G06F9/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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