| 摘要 |
An A/D converter (2) supplies an interpolation circuit (3) with sampled values which are obtained by sampling a playback signal coming from a read-out device (1) in synchronization with a system clock signal. In the interpolation circuit (3), the value of the playback signal at the time the phase of a PLL clock phase signal P supplied by a PLL clock phase signal generator (7) becomes zero is computed from the sampled values by using a linear interpolation technique. The interpolation value is then supplied to a binary conversion circuit (4) and fed back to a phase error detecting circuit (5). The binary conversion (4) circuit converts the interpolation value of the playback signal into a binary value which is then supplied to a circuit at the following stage. The phase error detecting circuit (5) detects a zero cross of the interpolation value of the playback signal. The zero cross timing is then used for computing a phase error signal which is then output to the PLL clock phase signal generator (7) by way of a loop filter (6). The PLL clock phasesignal generator generates the PLL clock phase signal P which is supplied to the interpolation circuit as described above. <IMAGE> |
