| 摘要 |
A microprocessor (5) including a plurality of arithmetic logic units (42) is disclosed. At least one of the arithmetic logic units (42) includes a shifter circuit (50) for executing logical and arithmetic shift, rotate, and rotate-through-carry instructions in both the left and right directions, on data words of various lengths. The shifter (50) includes a series of input multiplexers (72, 74, 76, 78) for presenting the data word, carry bits, and extended sign bits to a first funnel shifter stage (80). Each of the multiplexers (72, 74, 76, 78) and first funnel shifter stage (80) are preferably realized by AND-OR-INVERT logic, to allow for 0 logic states and don't cares to be presented by the nonassertion of a control signal thereto. The shifter (50) is implemented as a right funnel shifter, with left shifts and rotates performed by presentation of the data word to the most significant bits of the first funnel shifter stage (80), followed by a right shift of the logical complement of the shift count. The first funnel shifter stage (80) is controlled by logic (84) that enforces a single bit position shift if the shift or rotate is in the left direction, contemplating at least the least significant bit of the shift count. A second funnel shifter stage (82) is provided to complete the shift or rotate execution by the most significant bits of the shift count, presented as the logical complement if the shift is in the left direction.
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