发明名称 |
Integrated processing and L2 DRAM cache |
摘要 |
An integrated processor and level two (L2) dynamic random access memory (DRAM) are fabricated on a single chip. As an extension of this basic structure, the invention also contemplates multiprocessor "node" chips in which multiple processors are integrated on a single chip with L2 cache. By integrating the processor and L2 DRAM cache on a single chip, high on-chip bandwidth, reduced latency and higher performance are achieved. A multiprocessor system can be realized in which a plurality of processors with integrated L2 DRAM cache are connected in a loosely coupled multiprocessor system. Alternatively, the single chip technology can be used to implement a plurality of processors integrated on a single chip with an L2 DRAM cache which may be either private or shared. This approach overcomes a number of issues which limit the performance and cost of a memory hierarchy. When the L2 DRAM cache is placed on the same chip as the processor, the time needed for two chip-to-chip crossings is eliminated. Since these crossings require off-chip drivers and receivers and must be synchronized with the system clock, the time involved is substantial. This means that with the integrated L2 DRAM cache, latency is reduced.
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申请公布号 |
US5895487(A) |
申请公布日期 |
1999.04.20 |
申请号 |
US19960748300 |
申请日期 |
1996.11.13 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BOYD, WILLIAM TODD;HELLER, JR., THOMAS JAMES;IGNATOWSKI, MICHAEL;MATICK, RICHARD EDWARD;SCHUSTER, STANLEY EVERETT |
分类号 |
G06F12/08;G06F15/78;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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