发明名称 |
Clock extraction circuit |
摘要 |
<p>Disclosed is a clock extraction circuit for extracting a clock signal which furnishes timing for discriminating a data signal, from the data signal. The clock extraction circuit has a timing extraction unit for extracting the clock signal from the data signal, and a filter, which is provided in front of the timing extraction unit, having an upper limited frequency sufficiently lower than the bit rate of the data. The data signal is input to the timing extraction unit via the filter. <IMAGE></p> |
申请公布号 |
EP0910192(A2) |
申请公布日期 |
1999.04.21 |
申请号 |
EP19980106183 |
申请日期 |
1998.04.03 |
申请人 |
FUJITSU LIMITED |
发明人 |
SAKAMOTO, HISAYA;SUGATA, AKIHIKO;MIYAZAKI, AKIMITSU;KIYONAGA, TETSUYA |
分类号 |
H03K5/04;H03K5/00;H04L7/027;H04L7/033;(IPC1-7):H04L7/00 |
主分类号 |
H03K5/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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