发明名称 |
Data output control circuit for semiconductor memory device |
摘要 |
A data output control circuit for a semiconductor memory device sequentially transmits input data via a main amplifier controlled by an address transition detecting signal, a multiplex/latch unit, a data output buffer and an output operator. The data output control circuit prevents false data output, which also improves data processing speed by using a control signal. The data output control circuit includes an output control unit that converts an address transition detecting signal into a kill signal. The kill signal is applied to the data output buffer to cause the output operator to generate a zero level signal based on the address transition detecting signal. The data output control circuit enables the output operator to generate a zero level signal by applying the kill signal to the data output buffer when the transition of an address signal is detected. Accordingly, an interval for a data reversal or a full swing is prevented to enhance data processing speed and reduce current consumption.
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申请公布号 |
US5896323(A) |
申请公布日期 |
1999.04.20 |
申请号 |
US19970900340 |
申请日期 |
1997.07.25 |
申请人 |
LG SEMICON CO., LTD. |
发明人 |
PARK, YI HWAN;SHIN, HYUN SOO |
分类号 |
G11C11/41;G11C7/10;G11C11/407;G11C11/409;G11C11/413;(IPC1-7):G11C16/04 |
主分类号 |
G11C11/41 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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