Initializing and reprogramming circuitry for state independent memory array burst operations control

摘要

A synchronous dynamic random access memory (SDRAM) device having a master control circuit for accepting a first command and a second command and having an initialization and reprogramming circuit. The master control circuit generates and initialization signal in response to the first command and generates a reprogramming signal in response to the second command. The initialization and reprogramming circuit responds to the initialization signal to control initial programming of a burst control operation feature and responds to the reprogramming signal to control a reprogramming of the burst control operation feature.