| 摘要 |
In a DRAM column decoder, an OR gate receiving a test signal and an output of a column decoder unit circuit is provided corresponding to each column select line. When test signal is at the active "H" level, all column select lines attain the "H" level and all column select gates are rendered conductive, allowing collective writing row by row. A separate circuit for collective writing is not required, so that the layout area is reduced.
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