| 摘要 |
To minimize the number of fuses for the block write redundancy discrimination, a semiconductor memory of the invention having a block write function of eight columns comprises; a first and a second memory cell array (MCA1 and MCA2) both driven by a common row decoder (RD1), logic of LSB (Y0) of the column address of the first memory cell array being '0' and that of the second memory cell array being '1', a first and a second column decoders (CD1 and CD2), and a first and a second column redundancy discrimination circuits (CRD1 and CRD2), each controlling corresponding each of the first and the second column decoders to replace data write into a defective column address by data write to a redundant column address, by watching logic of higher bits (Y3 to Y7) and corresponding half of eight column mask signals (CM0 to CM7) in a block write mode.
|
