发明名称 Level shifting circuit for memory circuit e.g. DRAM
摘要 The circuit includes an inverter (INV31), four PMOS transistors (PM31-34) and four NMOS transistors (NM31-34). If a first input signal is a selected block signal, and a second input signal is a select signal for a block connected to a sense amplifier, then the first input signal becomes a high level if a memory circuit is blocked, and become a low level when the memory circuit is released.
申请公布号 DE19825034(A1) 申请公布日期 1999.04.15
申请号 DE19981025034 申请日期 1998.06.04
申请人 LG SEMICON CO., LTD., CHEONGJU, KR 发明人 KIM, KYUNG-WOL, SEOUL, KR
分类号 H03K19/0185;G11C7/10;G11C11/40;G11C11/409;H03K3/356;(IPC1-7):G11C7/00;H03K19/018 主分类号 H03K19/0185
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