发明名称 Verfahren zum Ätzen eines Verbundhalbleiters
摘要 Semiconductor device fabrication comprises providing a workpiece (12) including a III-V cpd. semiconductor surface in a reactor (10) and etching in a pulsed mode including spaced intervals in which an etchant gas (16) is introduced. In the intervals between the etchant a gas including a gp. III constituent which is capable of migrating along the surface is introduced into the reactor (20), and a semiconductor layer is grown on the surface in-situ after etching.
申请公布号 DE69505022(T2) 申请公布日期 1999.04.15
申请号 DE1995605022T 申请日期 1995.02.08
申请人 AT&T CORP., NEW YORK, N.Y., US 发明人 CHIU, TIEN-HENG, SPOTSWOOD, NEW JERSEY 08884, US;TSANG, WON-TIEN, HOLMDEL, NEW JERSEY 07733, US
分类号 C23F4/00;C30B25/02;H01L21/20;H01L21/203;H01L21/205;H01L21/302;H01L21/3065;(IPC1-7):H01L21/20;H01L21/306;C30B25/14 主分类号 C23F4/00
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