| 摘要 |
A pattern generator facilitates the pattern generation of an electronics device to be measured such as SDRAM where each input and output signal cycle is not matched. The pattern generator includes a first address signal delay section that applies a cycle delay to a first address signal based on the number set in a first delay register, a second address signal delay section that applies a cycle delay to a second address signal based on the number set in a second delay register, a data signal delay section that applies a cycle delay to a data signal based on the number set in a data delay register, a control signal delay section that applies cycle delay to a control signal based on the number set in a control delay register. |
