Dual damascene with self aligned via interconnects

摘要

An improved method of performing a dual damascene etch through a layer stack disposed above a substrate using self aligned vias. The layer stack includes an underlying conductive layer and an insulating layer disposed above the underlying conductive layer. The method includes the following operative steps. A layer of hard resist is deposited upon a top surface of the insulating layer patterned such that a first opening in the hard resist layer is positioned over the underlying device layer. A layer of soft resist is then deposited upon the top surface of the hard resist, the soft resist has a second opening smaller than and aligned to the first opening and the underlying conductive layer. A first trench is then formed in the top surface of the insulating layer positioned over and separated from the underlying device layer by insulating material at a bottom of the trench. The soft resist is then removed without substantially affecting the hard resist. The via is formed by etching through the insulator material at the bottom of the trench down to the underlying device layer. <IMAGE>