| 摘要 |
<p>A FIR filter for programmable decimation by powers of two has an input coupled to receive an input signal and an output coupled to the input. The FIR filter uses context registers, where the number of contexts per context register is equal to the maximum desired decimation power m. An output context register coupled to provide the output simultaneously contains all of the decimation output results, the desired decimation result being selected as one of the output contexts. A cascade of timing circuits in response to an initial clock signal and an initial valid signal at one-half the frequency of the initial clock signal provide timing signals for storing the decimation results as separate contexts in each context register. At any time any desired decimation result is available for output. <IMAGE></p> |
