| 摘要 |
<p>PROBLEM TO BE SOLVED: To obtain a receiver in which much adjusting time and many adjusting components are not required by a method wherein a plurality of latch means which hold and output respective outputs of a plurality of A/D conversion means and a timing adjusting means are provided in respective signal routes between the plurality of A/D conversion means and a signal processing means. SOLUTION: Registers 41a, 41b as latch means which hold respective outputs of A/D converters 12a, 12b are interposed in respective signal routes between the A/D converters 12a, 12b and a signal processing circuit 13. Then, the A/D converters 12a, 12b and the registers 41a, 41b are timing-adjusted independently of each other by a clock delay circuit 42 as a timing adjusting means. The clock delay circuit 42 supplies, to the A/D converters 12a, 12b and the registers 41a, 41b, clock signals 3 to 6 whose timing is different from each other. Thereby, outputs of the respective A/D converters 12a, 12b can be set at an identical amplitude and an identical signal length.</p> |
