| 摘要 |
<p>PROBLEM TO BE SOLVED: To prevent malfunction even if deviation in timing due to changes of source voltage and temperature conditions is generated by extracting the degree of delay of timing varying owing to variation in source voltage, etc., in operation and gate delay and selecting as a clock frequency a frequency corresponding to the degree of the delay. SOLUTION: A delay detecting circuit 2, register circuits 5a and 5b, and a CPU 10 constitute a delay detection control means; and the delay detecting circuit 2 mainly detects the delay of a signal and the CPU 10 mainly controls other circuits. Then the delay detecting circuit 2 inputs the reference frequency signal from an oscillation circuit 1 and extracts the degree of delay of the timing varying owing to variation in source voltage and temperature in operation and gate delay and wiring delay and selects as the clock frequency the frequency corresponding to the degree of delay to control clock oscillation. Consequently, normal operaton can be maintained even if deviation in the timing is caused in operation only by considering the operation margin, based upon the voltage and temperature, in the case of LSI designing.</p> |
