| 摘要 |
PROBLEM TO BE SOLVED: To reduce wiring resistance and contact resistance by defining a memory cell portion as a non-silicide region and also defining a logical circuit region including a peripheral circuit region other than the memory cell or the peripheral region as a silicide region. SOLUTION: For example, in a transistor element formed in a logic circuit forming region (including a peripheral circuit region) which is a silicide region 2, a semiconductor device selectively forms silicide layers 8, 9 on the surface of a gate electrode 5 and a source/drain region 7. Thereby, a low resistance of gate electrode 5, namely word line and also low resistance of contact resistance of a contact 12 formed in the condition being connected to the source/ drain region 7 can be realized. Moreover, since a sidewall is not formed at the sidewall of the gate electrode 6 forming a transistor element of a non-silicide region 1 for controlling junction leakage by controlling the formation of the silicide, damages from etching given to the surface of a semiconductor substrate 3 can be reduced. |
