| 摘要 |
PROBLEM TO BE SOLVED: To perform acceleration processing of conversion processing regardless of compressibility of code data by parallelly processing a data set that consists of plural code data and size data. SOLUTION: A FIFO register 12 writes 20-bit data set that consists of code data CODE of 16-bit length which includes effective bits of 1 to 16-bit length which are supplied and size data SIZE of 4-bit length which represents its effective bit length under the control of a FIFO controller 14 and temporarily stores it. Also, the data set is inputted to the controller 14 and is written to the register 12 in response to a control signal from a control circuit 20 in order of registers 12a to 12d. In this way, plural code data CODE and size data SIZE are parallelly processed, and 1 to 16-bit length effective bits that are shown by each corresponding size data SIZE are simultaneously taken out from plural code data CODE. They are converted into 8-bit length data and accelerated regardless of compressibility. |
