| 摘要 |
PROBLEM TO BE SOLVED: To reduce the number of transistors and to improve an operation speed and the degree of integration by making an output a flip-flop which has a transfer gate of one transistor and a latch function of two inverters. SOLUTION: When a clock signalϕck changes from low to high, transistors QN1 and QN2 are turned on, and an output signalϕout becomes low from high after a node N6 is shifted from low to high. Next, when the signalϕck becomes low from high, the transistors QN1 and QN2 are turned off, and during this time, current I1 flows as stationary current. Here, the current drive capability of a 2nd CMOS inverter consisting of transistors QP8 and QN4 is set to <=1/5 of the transistor QN2, and the current consumption of the 2nd CMOS inverter at the time of change of the signalϕout is suppressed. It is possible to perform acceleration from the time when the signalϕck shifts from low to high until the signalϕout changes.
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