| 摘要 |
<p>An integrated circuit tester (figure 1), for implementing a succession of timed test events at terminals of an integrated circuit device under test (12), includes a set of N channels (CH(1)-Ch(n)). Each of the channels includes at least one timing signal generator (18 or 19) for producing an output timing signal for triggering various types of test events carried out by the tester channel. At the start of each cycle of a test, each timing signal generator receives input timing data referencing a time at which a test event is to occur and also receives input format data indicating the format of that test event. Each timing signal generator then generates its output timing signal before the event time referenced by the timing data with a lead time selected by the input format data. Each timing signal generator may be independently calibrated such that the format data always selects the appropriate lead time for the event to be triggered so that each type of event occurs at the time indicated by the input timing data regardless of the nature of the event being triggered.</p> |
