发明名称 |
Combined consective byte update buffer |
摘要 |
An apparatus and method for minimizing bus traffic by combining write operations is disclosed. The present invention detects the occurrence of consecutive byte updates to a common 32-bit block. This is accomplished by using comparators to examine the addresses of consecutive write operations. If it is determined that the consecutive write operations are indeed to a common 32-bit block, they are combined. The address of the next write operation is also, similarly checked. All of the writes into that particular block are combined in a write combine register. The contents of this register is then transferred to a write buffer. When bus access is granted, the combined byte updates stored in the write buffer are issued in a single memory write cycle to the bus, thereby minimizing the number of write cycles actually required to transfer the data.
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申请公布号 |
US5892978(A) |
申请公布日期 |
1999.04.06 |
申请号 |
US19960685809 |
申请日期 |
1996.07.24 |
申请人 |
VLSI TECHNOLOGY, INC. |
发明人 |
MUNGUIA, GABRIEL R.;GARINGER, NED D.;RICHARDSON, NICHOLAS J. |
分类号 |
G06F13/28;(IPC1-7):G06F13/00 |
主分类号 |
G06F13/28 |
代理机构 |
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主权项 |
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地址 |
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