发明名称 |
Method of reducing fringe capacitance |
摘要 |
A method of reducing the fringe capacitance between a gate and a substrate in a semiconductor device. A silicon nitride is formed over a substrate with a buffer oxide layer thereon and patterned to form an opening. The buffer oxide layer within the opening is removed and another oxide layer is formed at the same place as a gate oxide layer. A poly-gate is formed at the opening with a wider width than the opening. Thus, a part of the poly-gate at both ends covers a part of the silicon nitride layer. The silicon nitride layer is then removed and leaves the poly-gate as a T-shape with two ends suspended over the substrate. With a large angle, a light dopant is implanted into the substrate under the suspended part of the poly-gate to form a lightly doped region. With another smaller angle, a heavy dopant is implanted into the substrate beside the poly-gate. Therefore, a source/drain is formed. A undoped silicate glass layer and a borophosphosilicate layer are formed in sequence, and an air gap is formed between the suspended part of the poly-gate and the substrate.
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申请公布号 |
US5891783(A) |
申请公布日期 |
1999.04.06 |
申请号 |
US19970927323 |
申请日期 |
1997.09.11 |
申请人 |
UNITED SEMICONDUCTOR CORP. |
发明人 |
LIN, CHIH-HUNG;CHOU, JIH-WEN |
分类号 |
H01L21/28;H01L21/336;H01L29/423;H01L29/49;H01L29/78;(IPC1-7):H01L21/336 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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