| 摘要 |
An parallel test circuit for memory device is provided. The parallel test circuit according to the present invention includes: a plurality of memory mats, wherein each of memory mats comprises a memory cell for writing two-bit data and an X, Y address decoder for accessing the memory cell; a amplifying unit having a plurality of main amplifiers, wherein each of main amplifiers compares and amplifies a voltage difference between two-bit data of corresponding memory cell, and thereby output one-bit logic value; a data reducing unit for reducing a plurality of logic value from the amplifying unit to one-bit logic value. Accordingly, the parallel test circuit according to the present invention improves test efficiency twice by which a single main amplifier compares and amplifies two-bit data.
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