发明名称 Method and apparatus for optimizing dependent operand flow within a multiplier using recoding logic
摘要 A method and apparatus for eliminating the setup time typically required for Booth recoding logic is provided. Interlock circuitry detects when a second multiply instruction specifies that the product of a previous multiply instruction is to be used as the multiplier input to the Booth recoding logic. The interlock logic controls mux inputs to both the multiplier path, and the multiplicand path. When the interlock logic detects such a multiplier dependency, the product of the previous multiply instruction is provided to the multiplicand path, and the multiplicand is provided to the multiplier path. The multiplier for the second multiply instruction can therefore be provided to the Booth recoding logic, before the product of the previous multiply instruction is available. The Booth recoding logic is therefore setup, prior to execution of the second multiply instruction.
申请公布号 US5892699(A) 申请公布日期 1999.04.06
申请号 US19970931859 申请日期 1997.09.16
申请人 INTEGRATED DEVICE TECHNOLOGY, INC. 发明人 DUNCAN, JOHN L.;LOPER, JR., ALBERT J.
分类号 G06F7/52;(IPC1-7):G06F7/52 主分类号 G06F7/52
代理机构 代理人
主权项
地址