PLL synthesizer apparatus

摘要

Disclosed herein is a fractional N-type PLL frequency synthesizer apparatus. A fractional N-type control circuit employed therein for varying N values for each reference cycle is constructed of a combination of a frequency divider (comprising D flip-flops) and a logic circuit (comprising an exclusive OR circuit, AND circuits and an OR circuit), taking the timing provided to output a carry signal into consideration in advance. Owing to such a construction, the fractional N-type PLL frequency synthesizer apparatus can be activated with low noise and can provide a short lockup time.