发明名称 |
Packaging design system for an LSI circuit |
摘要 |
A packaging design system for an LSI circuit includes: a gate placement preparation unit for preparing basic placement data for gates used as an original data for producting the LSI circuit; a wiring data preparation unit operatively connected to the gate placement preparation unit for preparing wiring data based on wiring patterns each having the same length between gates; a delay calculation unit operatively connected to the wiring data preparation unit for calculating net delays between gates and path delays from a clock input until an output in the LSI circuit; a standard path delay determining unit operatively connected to the delay calculation unit for determining a standard path delay in accordance with distribution of path delays; and a macro determining unit operatively connected to the standard path delay determining unit for selecting the macros in accordance with predetermined conditions of path delays, and selected several macros being used for an actual placement of gates.
|
申请公布号 |
US5892685(A) |
申请公布日期 |
1999.04.06 |
申请号 |
US19960669766 |
申请日期 |
1996.06.25 |
申请人 |
FUJITSU LIMITED |
发明人 |
SUGIYAMA, HIROYUKI;MARUYAMA, TERUNOBU;YAMASHITA, RYOUICHI |
分类号 |
G06F17/50;(IPC1-7):G06F17/00 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|