Redundancy circuit technique applied to DRAM of multi-bit I/O having overlaid-DQ bus

摘要

There is provided a semiconductor memory device of a overlaid-DQ system having a column redundancy technique having high efficiency of replacing a defective address without largely increasing a chip size. Regarding DRAM of the overlaid-DQ bus type, in a metal line layer formed at an upper portion than bit lines, 256 pairs of DQ lines (DQ0 to DQ255) are formed in a form to be overlaid on the memory cell array. Each of spare circuits (a spare column, its sense amplifier (S/A), a pair of spare DQ lines (pair of SDQ lines SDQ0 to SDQ3)) is arranged per 64 pairs of DQ lines. Four sets of spare circuits may be structured as a column redundancy in connection with the 256 pairs of DQ lines, each set of spare circuits may be structured in connection with 65 pairs of DQ lines.